RL

Reed Linde

OP Optimal Plus: 7 patents #3 of 18Top 20%
OP Optimaltest: 3 patents #3 of 6Top 50%
IN Intel: 2 patents #13,213 of 30,777Top 45%
Overall (All Time): #401,892 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11919046 System and method for binning at final test Gill Balog 2024-03-05
11235355 System and method for binning at final test Gill Balog 2022-02-01
10118200 System and method for binning at final test Gil Balog 2018-11-06
9529036 Systems and methods for test time outlier detection and correction in integrated circuit testing Gil Balog, Avi Golan 2016-12-27
8872538 Systems and methods for test time outlier detection and correction in integrated circuit testing Gil Balog, Avi Golan 2014-10-28
8838408 Misalignment indication decision system and method Dan GLOTTER, Alexander Chufarovsky, Leonid Gurov 2014-09-16
8781773 System and methods for parametric testing Leonid Gurov, Alexander Chufarovsky, Gil Balog 2014-07-15
8421494 Systems and methods for test time outlier detection and correction in integrated circuit testing Gil Balog, Avi Golan 2013-04-16
7969174 Systems and methods for test time outlier detection and correction in integrated circuit testing Gil Balog, Avi Golan 2011-06-28
7528622 Methods for slow test time detection of an integrated circuit during parallel testing Gil Balog, Avi Golan 2009-05-05
7405586 Ultra low pin count interface for die testing Sunil Gupta, Rich Fackenthal 2008-07-29
7177189 Memory defect detection and self-repair technique Alec W. Smidt 2007-02-13