RS

Ramesh Sathianathan

MG Mentor Graphics: 7 patents #40 of 698Top 6%
📍 Sunnyvale, CA: #3,068 of 14,302 inventorsTop 25%
🗺 California: #66,801 of 386,348 inventorsTop 20%
Overall (All Time): #570,934 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
9684760 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2017-06-20
9262557 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2016-02-16
9117044 Hierarchical verification of clock domain crossings Ka Kei Kwok, Priya Viswanathan, Rojer Raji Sabbagh 2015-08-25
8819599 Hierarchical verification of clock domain crossings Ka Kei Kwok, Priya Viswanathan, Rojer Raji Sabbagh 2014-08-26
8418121 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2013-04-09
7890897 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2011-02-15
7454324 Selection of initial states for formal verification James Andrew Garrard Seawright, Christophe Gauthron, Jeremy Rutledge Levitt, Kalyana C. Mulam, Chian-min Richard Ho +1 more 2008-11-18
7318205 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2008-01-08
6848088 Measure of analysis performed in property checking Jeremy Rutledge Levitt, Christophe Gauthron, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam 2005-01-25