Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9483594 | Reset verification | Ping Fai Yeung, Priya Viswanathan | 2016-11-01 |
| 9117044 | Hierarchical verification of clock domain crossings | Priya Viswanathan, Rojer Raji Sabbagh, Ramesh Sathianathan | 2015-08-25 |
| 8914761 | Metastability effects simulation for a circuit description | Tai A. Ly, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr. | 2014-12-16 |
| 8819599 | Hierarchical verification of clock domain crossings | Priya Viswanathan, Rojer Raji Sabbagh, Ramesh Sathianathan | 2014-08-26 |
| 8438516 | Metastability effects simulation for a circuit description | Tai A. Ly, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr. | 2013-05-07 |
| 8271918 | Formal verification of clock domain crossings | Bing Li, Tai A. Ly, Rojer Raji Sabbagh | 2012-09-18 |
| 7454728 | Metastability injector for a circuit description | Tai A. Ly, Vijaya Vardhan Gupta, Ross Andrew Andersen, Ping Fai Yeung, Neil Hand +1 more | 2008-11-18 |
| 7356789 | Metastability effects simulation for a circuit description | Tai A. Ly, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr. | 2008-04-08 |
| 7243322 | Metastability injector for a circuit description | Tai A. Ly, Vijaya Vardhan Gupta, Ross Andrew Ander, Ping Fai Yeung, Neil Hand +1 more | 2007-07-10 |