Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8060847 | Clock model for formal verification of a digital circuit description | Jeremy Rutledge Levitt, Christophe Gauthron | 2011-11-15 |
| 7487483 | Clock model for formal verification of a digital circuit description | Jeremy Rutledge Levitt, Christophe Gauthron | 2009-02-03 |
| 7454324 | Selection of initial states for formal verification | Ramesh Sathianathan, Christophe Gauthron, Jeremy Rutledge Levitt, Kalyana C. Mulam, Chian-min Richard Ho +1 more | 2008-11-18 |
| 6421815 | Method and apparatus for optimized partitioning of finite state machines synthesized from hierarchical high-level descriptions | — | 2002-07-16 |
| 4696554 | Method and apparatus for providing a variable multiple image visual effect | — | 1987-09-29 |