Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10756738 | JTL-based superconducting logic arrays and FPGAS | William Robert Reohr, Randall M. Burnett | 2020-08-25 |
| 10541024 | Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines | Randall M. Burnett, Haitao O. Dai, Quentin P. Herr | 2020-01-21 |
| 10447278 | JTL-based superconducting logic arrays and FPGAs | William Robert Reohr, Randall M. Burnett | 2019-10-15 |
| 7991955 | Method and apparatus to achieve more level thermal gradient | Michael D. Bienek, Victor F. Andrade, Michael C. Braganza | 2011-08-02 |
| 7417449 | Wafer stage storage structure speed testing | Michael Kevin Ciraula | 2008-08-26 |
| 7355881 | Memory array with global bitline domino read/write scheme | Floyd L. Dankert, Victor F. Andrade, Michael Kevin Ciraula, Alexander W. Schaefer, Jerry D. Moench +4 more | 2008-04-08 |