Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6202142 | Microcode scan unit for scanning microcode instructions using predecode data | Shane Southard, Thang M. Tran | 2001-03-13 |
| 6161172 | Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor | Rupaka Mahalingaiah, Paul K. Miller | 2000-12-12 |
| 6148393 | Apparatus for generating a valid mask | Thang M. Tran, Shane Southard | 2000-11-14 |
| 6085311 | Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch | Venkateswara Madduri | 2000-07-04 |
| 6076146 | Cache holding register for delayed update of a cache line into an instruction cache | Thang M. Tran, Karthikeyan Muthusamy, Andrew McBride | 2000-06-13 |
| 6049863 | Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor | Thang M. Tran, Andrew McBride, Karthikeyan Muthusamy | 2000-04-11 |
| 5983321 | Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache | Thang M. Tran, Karthikeyan Muthusamy, Andrew McBride | 1999-11-09 |
| 5968163 | Microcode scan unit for scanning microcode instructions using predecode data | Shane Southard, Thang M. Tran | 1999-10-19 |
| 5951675 | Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch | Venkateswara Madduri | 1999-09-14 |
| 5940602 | Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations | Thang M. Tran | 1999-08-17 |
| 5935239 | Parallel mask decoder and method for generating said mask | — | 1999-08-10 |
| 5900013 | Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries | Karthikeyan Muthusamy | 1999-05-04 |
| 5898851 | Method and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operations | Thang M. Tran | 1999-04-27 |
| 5884058 | Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor | Rupaka Mahalingaiah, Paul K. Miller | 1999-03-16 |
| 5875315 | Parallel and scalable instruction scanning unit | — | 1999-02-23 |
| 5872947 | Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions | — | 1999-02-16 |
| 5872946 | Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch | Venkateswara Madduri | 1999-02-16 |
| 5867680 | Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions | Rupaka Mahalingaiah, Paul K. Miller | 1999-02-02 |
| 5859991 | Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method | — | 1999-01-12 |
| 5859992 | Instruction alignment using a dispatch list and a latch list | Thang M. Tran, Jagadish V. Nayak | 1999-01-12 |
| 5852727 | Instruction scanning unit for locating instructions via parallel scanning of start and end byte information | Thang M. Tran | 1998-12-22 |
| 5850532 | Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched | Shane Southard, Thang M. Tran | 1998-12-15 |
| 5826071 | Parallel mask decoder and method for generating said mask | — | 1998-10-20 |
| 5822559 | Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions | Thang M. Tran | 1998-10-13 |
| 5781789 | Superscaler microprocessor employing a parallel mask decoder | — | 1998-07-14 |