Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10042804 | Multiple protocol engine transaction processing | Charles Edward Watson, Jr., David B. Glasco | 2018-08-07 |
| 8930636 | Relaxed coherency between different caches | Joel J. McCormack, Olivier Giroux, Emmett M. Kilgariff | 2015-01-06 |
| 8898254 | Transaction processing using multiple protocol engines | Charles Edward Watson, Jr., David B. Glasco | 2014-11-25 |
| 8572206 | Transaction processing using multiple protocol engines | Charles Edward Watson, Jr., David B. Glasco | 2013-10-29 |
| 8185602 | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters | Charles Edward Watson, Jr., David B. Glasco | 2012-05-22 |
| 7577727 | Dynamic multiple cluster system reconfiguration | Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco | 2009-08-18 |
| 7577755 | Methods and apparatus for distributing system management signals | Carl Zeitler, David B. Glasco, Les Record, Richard R. Oehler, William G. Kulpa +1 more | 2009-08-18 |
| 7418517 | Methods and apparatus for distributing system management signals | Carl Zeitler, David B. Glasco, Les Record, Richard R. Oehler, William G. Kulpa +1 more | 2008-08-26 |
| 7395347 | Communication between and within multi-processor clusters of multi-cluster computer systems | Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco | 2008-07-01 |
| 7386626 | Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems | Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco | 2008-06-10 |
| 7366879 | Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses | Dion Rodgers, Darrell D. Boggs, Amit Merchant, Rachel Hsu | 2008-04-29 |
| 7353370 | Method and apparatus for processing an event occurrence within a multithreaded processor | Dion Rodgers, Darrell D. Boggs, Amit Merchant, Rachel Hsu, Keshavan Tiruvallur | 2008-04-01 |
| 7296121 | Reducing probe traffic in multiprocessor systems | Eric Morton, Adnan Khaleel, David B. Glasco | 2007-11-13 |
| 7281055 | Routing mechanisms in systems having multiple multi-processor clusters | David B. Glasco, Carl Zeitler, Guru Prasadh, Richard R. Oehler | 2007-10-09 |
| 7251698 | Address space management in systems having multiple multi-processor clusters | David B. Glasco, Carl Zeitler, Guru Prasadh, Richard R. Oehler | 2007-07-31 |
| 7222262 | Methods and devices for injecting commands in systems having multiple multi-processor clusters | Guru Prasadh, David B. Glasco, Scott S. Diesing | 2007-05-22 |
| 7162589 | Methods and apparatus for canceling a memory data fetch | David B. Glasco | 2007-01-09 |
| 7159137 | Synchronized communication between multi-processor clusters of multi-cluster computer systems | Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco | 2007-01-02 |
| 7155525 | Transaction management in systems having multiple multi-processor clusters | David B. Glasco, Carl Zeitler, Guru Prasadh, Richard R. Oehler | 2006-12-26 |
| 7117419 | Reliable communication between multi-processor clusters of multi-cluster computer systems | Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco | 2006-10-03 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems | Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco | 2006-09-05 |
| 7069392 | Methods and apparatus for extended packet communications between multiprocessor clusters | Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco | 2006-06-27 |
| 7047372 | Managing I/O accesses in multiprocessor systems | Carl Zeitler, David B. Glasco, Guru Prasadh, Richard R. Oehler, David Edrich | 2006-05-16 |
| 7039794 | Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor | Dion Rodgers, Darrell D. Boggs, Amit Merchant, Rachel Hsu, Keshavan Tiruvallur | 2006-05-02 |
| 6934814 | Cache coherence directory eviction mechanisms in multiprocessor systems which maintain transaction ordering | David B. Glasco, Sridhar K. Valluru | 2005-08-23 |