Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7120073 | Integrated circuit devices having reducing variable retention characteristics | Russell L. Meyer | 2006-10-10 |
| 7069484 | System for optimizing anti-fuse repair time using fuse id | — | 2006-06-27 |
| RE38956 | Data compression circuit and method for testing memory devices | Leland R. Nevill, Neil L. Hansen, Eugene H. Cloud | 2006-01-31 |
| 6898138 | Method of reducing variable retention characteristics in DRAM cells | Russell L. Meyer | 2005-05-24 |
| 6625073 | Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices | — | 2003-09-23 |
| 6622270 | System for optimizing anti-fuse repair time using fuse ID | — | 2003-09-16 |
| 6477662 | Apparatus and method implementing repairs on a memory device | William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2002-11-05 |
| 6442719 | Method and apparatus for detecting intercell defects in a memory device | William K. Waller | 2002-08-27 |
| 6347386 | System for optimizing the testing and repair time of a defective integrated circuit | — | 2002-02-12 |
| 6233185 | Wafer level burn-in of memory integrated circuits | Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller | 2001-05-15 |
| 6181154 | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | — | 2001-01-30 |
| 6145092 | Apparatus and method implementing repairs on a memory device | William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2000-11-07 |
| 6128756 | System for optimizing the testing and repair time of a defective integrated circuit | — | 2000-10-03 |
| 6119251 | Self-test of a memory device | Eugene H. Cloud, Leland R. Nevill, Warren M. Farnworth | 2000-09-12 |
| 6094734 | Test arrangement for memory devices using a dynamic row for creating test data | Eugene H. Cloud, Leland R. Nevill, Ken Waller, Warren M. Farnworth | 2000-07-25 |
| 6079037 | Method and apparatus for detecting intercell defects in a memory device | William K. Waller | 2000-06-20 |
| 6058056 | Data compression circuit and method for testing memory devices | Leland R. Nevill, Neil L. Hansen, Eugene H. Cloud | 2000-05-02 |
| 6032264 | Apparatus and method implementing repairs on a memory device | William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2000-02-29 |
| 6003149 | Test method and apparatus for writing a memory array with a reduced number of cycles | Leland R. Nevill, Ken Waller, Eugene H. Cloud, Warren M. Farnworth | 1999-12-14 |
| 5982682 | Self-test circuit for memory integrated circuits | Leland R. Nevill, Warren M. Farnworth, Gene Cloud | 1999-11-09 |
| 5965902 | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | — | 1999-10-12 |
| 5966025 | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | — | 1999-10-12 |
| 5910921 | Self-test of a memory device | William K. Waller, Eugene H. Cloud, Warren M. Farnworth, Leland R. Nevill | 1999-06-08 |
| 5898629 | System for stressing a memory integrated circuit die | Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller | 1999-04-27 |
| 5885846 | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device | — | 1999-03-23 |