Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6647500 | System and method to generate a float voltage potential at output when first and second power supplies fail to supply power at the same time | — | 2003-11-11 |
| 6115290 | Mechanism for resetting sense circuitry to a known state in a nonvolatile memory device | — | 2000-09-05 |
| 6097637 | Dynamic single bit per cell to multiple bit per cell memory | Mark E. Bauer, Sanjay S. Talreja, Duane R. Mills, Rodney R. Rozman | 2000-08-01 |
| 5684752 | Pipelined read architecture for memory | Duane R. Mills, Sachidanandan Sambandan | 1997-11-04 |
| 5592435 | Pipelined read architecture for memory | Duane R. Mills, Sachidanandan Sambandan | 1997-01-07 |
| 5539690 | Write verify schemes for flash memory with multilevel cells | Sanjay S. Talreja, Mark E. Bauer, Kevin W. Frary | 1996-07-23 |
| 5523972 | Method and apparatus for verifying the programming of multi-level flash EEPROM memory | Mamun Ur Rashid, Mark E. Bauer, Chakravarthy Yarlagadda, Albert Fazio | 1996-06-04 |
| 5450363 | Gray coding for a multilevel cell memory system | Mark Christopherson, Steven Wells | 1995-09-12 |
| 5347484 | Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets | Sachidanandan Sambandan, Sherif Sweha, Duane R. Mills | 1994-09-13 |