Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11176302 | System on chip (SoC) builder | Sailesh Kumar, Pier Giorgio Raponi | 2021-11-16 |
| 10896476 | Repository of integration description of hardware intellectual property for NoC construction and SoC integration | Sailesh Kumar, Pier Giorgio Raponi | 2021-01-19 |
| 10749811 | Interface virtualization and fast path for Network on Chip | Joseph B. Rowlands, Joji Philip, Sailesh Kumar | 2020-08-18 |
| 10735335 | Interface virtualization and fast path for network on chip | Joseph B. Rowlands, Joji Philip, Sailesh Kumar | 2020-08-04 |
| 10547514 | Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation | Sailesh Kumar, Pier Giorgio Raponi | 2020-01-28 |
| 10523599 | Buffer sizing of a NoC through machine learning | Eric Norige, Sailesh Kumar | 2019-12-31 |
| 10469337 | Cost management against requirements for the generation of a NoC | William John Bainbridge, Eric Norige, Sailesh Kumar | 2019-11-05 |
| 10469338 | Cost management against requirements for the generation of a NoC | William John Bainbridge, Eric Norige, Sailesh Kumar | 2019-11-05 |
| 10419300 | Cost management against requirements for the generation of a NoC | William John Bainbridge, Eric Norige, Sailesh Kumar | 2019-09-17 |
| 10348563 | System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology | Sailesh Kumar, Pier Giorgio Raponi | 2019-07-09 |
| 10298485 | Systems and methods for NoC construction | Pier Giorgio Raponi, Sailesh Kumar | 2019-05-21 |
| 10084725 | Extracting features from a NoC for machine learning construction | Pier Giorgio Raponi, Sailesh Kumar | 2018-09-25 |
| 10063496 | Buffer sizing of a NoC through machine learning | Eric Norige, Sailesh Kumar | 2018-08-28 |