Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7941685 | Delay locked loop for an FPGA architecture | William C. Plants, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2011-05-10 |
| 7484113 | Delay locked loop for an FPGA architecture | William C. Plants, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2009-01-27 |
| 7171575 | Delay locked loop for and FPGA architecture | William C. Plants, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2007-01-30 |
| 6976185 | Delay locked loop for an FPGA architecture | William C. Plants, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2005-12-13 |
| 6718477 | Delay locked loop for an FPGA architecture | William C. Plants, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2004-04-06 |
| 5369643 | Method and apparatus for mapping test signals of an integrated circuit | Farid Rastgar, Sung-Soo Cho, Diane Bryant | 1994-11-29 |
| 4631427 | ECL gate circuit having internally generated reference voltages | David YEE | 1986-12-23 |
| 4628216 | Merging of logic function circuits to ECL latch or flip-flop circuit | — | 1986-12-09 |
| 4626709 | Dynamic push-pull for ECL | Frederick N. Lancia | 1986-12-02 |
| 4623803 | Logic level translator circuit for integrated circuit semiconductor devices having transistor-transistor logic output circuitry | Michael D. Thompson | 1986-11-18 |
| 4613774 | Unitary multiplexer-decoder circuit | — | 1986-09-23 |