Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12375205 | Systems and methods for performance monitoring with forward error correction mechanism | Arash Farhoodfar, Vlad Shyvdun, Michael Duckering, Devin Linnington | 2025-07-29 |
| 12204486 | Network transceiver with clock sharing between dies | Arash Farhoodfar, Srinivas Swaminathan, Belal Helal | 2025-01-21 |
| 11789662 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2023-10-17 |
| 11640836 | System and method for providing a configurable timing control for a memory system | Maher Amer, Claus Reitlingshoefer, Riccardo Badalone | 2023-05-02 |
| 11422749 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2022-08-23 |
| 11061841 | System and method for implementing a multi-threaded device driver in a computer system | Bart Trojanowski, Maher Amer | 2021-07-13 |
| 11062743 | System and method for providing a configurable timing control for a memory system | Maher Amer, Claus Reitlingshoefer, Riccardo Badalone | 2021-07-13 |
| 10942682 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2021-03-09 |
| 10725704 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2020-07-28 |
| 10719466 | System and method for implementing a multi-threaded device driver in a computer system | Bart Trojanowski, Maher Amer | 2020-07-21 |
| 10580465 | System and method for providing a configurable timing control for a memory system | Maher Amer, Claus Reitlingshoefer, Riccardo Badalone | 2020-03-03 |
| 10168954 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2019-01-01 |
| 9779020 | System and method for providing an address cache for memory map learning | Maher Amer, Riccardo Badalone | 2017-10-03 |
| 9575908 | System and method for unlocking additional functions of a module | Maher Amer, Riccardo Badalone | 2017-02-21 |
| 9552175 | System and method for providing a command buffer in a memory system | Maher Amer, Riccardo Badalone | 2017-01-24 |
| 9465557 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Maher Amer | 2016-10-11 |
| 9449651 | System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset | Maher Amer, Claus Reitlingshoefer | 2016-09-20 |
| 9444495 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2016-09-13 |
| 9088484 | Method and apparatus for preventing loops in a network by controlling broadcasts | Jimmy Ervin, James Alexander, Parveen Bhagwatula, Steven Faulkner | 2015-07-21 |
| 9015408 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Maher Amer | 2015-04-21 |
| 8972805 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2015-03-03 |
| 8738853 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Maher Amer | 2014-05-27 |
| 8713379 | System and method of interfacing co-processors and input/output devices via a main memory system | Maher Amer, Riccardo Badalone | 2014-04-29 |
| 8615599 | Method and apparatus for preventing loops in a network by controlling broadcasts | Jimmy Ervin, James Alexander, Parveen Bhagwatula, Steven Faulkner | 2013-12-24 |
| 8452917 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Maher Amer | 2013-05-28 |