| 11640836 |
System and method for providing a configurable timing control for a memory system |
Michael L. Takefman, Maher Amer, Riccardo Badalone |
2023-05-02 |
| 11062743 |
System and method for providing a configurable timing control for a memory system |
Michael L. Takefman, Maher Amer, Riccardo Badalone |
2021-07-13 |
| 10580465 |
System and method for providing a configurable timing control for a memory system |
Michael L. Takefman, Maher Amer, Riccardo Badalone |
2020-03-03 |
| 9449651 |
System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset |
Michael L. Takefman, Maher Amer |
2016-09-20 |
| 7902886 |
Multiple reference phase locked loop |
Dirk Pfaff, Stephen Hobbs |
2011-03-08 |
| 7796652 |
Programmable asynchronous first-in-first-out (FIFO) structure with merging capability |
Dirk Pfaff, Riccardo Badalone |
2010-09-14 |