Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11789662 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2023-10-17 |
| 11640836 | System and method for providing a configurable timing control for a memory system | Michael L. Takefman, Claus Reitlingshoefer, Riccardo Badalone | 2023-05-02 |
| 11422749 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2022-08-23 |
| 11061841 | System and method for implementing a multi-threaded device driver in a computer system | Bart Trojanowski, Michael L. Takefman | 2021-07-13 |
| 11062743 | System and method for providing a configurable timing control for a memory system | Michael L. Takefman, Claus Reitlingshoefer, Riccardo Badalone | 2021-07-13 |
| 10942682 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2021-03-09 |
| 10725704 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2020-07-28 |
| 10719466 | System and method for implementing a multi-threaded device driver in a computer system | Bart Trojanowski, Michael L. Takefman | 2020-07-21 |
| 10580465 | System and method for providing a configurable timing control for a memory system | Michael L. Takefman, Claus Reitlingshoefer, Riccardo Badalone | 2020-03-03 |
| 10168954 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2019-01-01 |
| 9779020 | System and method for providing an address cache for memory map learning | Michael L. Takefman, Riccardo Badalone | 2017-10-03 |
| 9575908 | System and method for unlocking additional functions of a module | Michael L. Takefman, Riccardo Badalone | 2017-02-21 |
| 9552175 | System and method for providing a command buffer in a memory system | Michael L. Takefman, Riccardo Badalone | 2017-01-24 |
| 9465557 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Michael L. Takefman | 2016-10-11 |
| 9449651 | System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset | Michael L. Takefman, Claus Reitlingshoefer | 2016-09-20 |
| 9444495 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2016-09-13 |
| 9015408 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Michael L. Takefman | 2015-04-21 |
| 8972805 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2015-03-03 |
| 8738853 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Michael L. Takefman | 2014-05-27 |
| 8713379 | System and method of interfacing co-processors and input/output devices via a main memory system | Michael L. Takefman, Riccardo Badalone | 2014-04-29 |
| 8452917 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Michael L. Takefman | 2013-05-28 |
| 8107357 | Optimized FFT/IFFT module | — | 2012-01-31 |
| 7917835 | Memory system and method for use in trellis-based decoding | — | 2011-03-29 |
| 7765457 | Parallel convolutional encoder | — | 2010-07-27 |
| 7623585 | Systems and modules for use with trellis-based decoding | — | 2009-11-24 |