Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11217298 | Delay-locked loop clock sharing | YoungHoon Oh | 2022-01-04 |
| 11158570 | Semiconductor devices having electrostatic discharge layouts for reduced capacitance | Eric J. Smith | 2021-10-26 |
| 11145354 | Apparatuses and methods to perform duty cycle adjustment with back-bias voltage | Myung-Ho Bae | 2021-10-12 |
| 10950291 | Apparatuses and methods to perform duty cycle adjustment with back-bias voltage | Myung-Ho Bae | 2021-03-16 |
| 10825506 | Systems and methods for improving output signal quality in memory devices | — | 2020-11-03 |
| 10790012 | Memory with a reduced array data bus footprint | Byung S. Moon | 2020-09-29 |
| 10747470 | Semiconductor device with pseudo flow through scheme for power savings | Ravi Kiran Kandikonda | 2020-08-18 |
| 10747693 | Semiconductor device with a time multiplexing mechanism for size efficiency | Ravi Kiran Kandikonda | 2020-08-18 |
| 10699774 | Mitigating line-to-line capacitive coupling in a memory die | Scott E. Smith | 2020-06-30 |
| RE47959 | Cascaded connection matrices in a distributed cross-connection system | Miriam Qunell, Jean-Michel Cala | 2020-04-21 |
| 10614870 | Low power method and system for signal slew rate control | Scott E. Smith | 2020-04-07 |
| 10580478 | Systems and methods for generating stagger delays in memory devices | — | 2020-03-03 |
| 10460791 | Systems and methods for generating stagger delays in memory devices | — | 2019-10-29 |
| 10438649 | Systems and methods for conserving power in signal quality operations for memory devices | — | 2019-10-08 |
| 10403353 | Systems and methods for reducing coupling noise between propagation lines for die size efficiency | Ravi Kiran Kandikonda | 2019-09-03 |
| 10395701 | Memory device with a latching mechanism | Vijayakrishna J. Vankayala | 2019-08-27 |
| 10366743 | Memory with a reduced array data bus footprint | Byung S. Moon | 2019-07-30 |
| 10157661 | Mitigating line-to-line capacitive coupling in a memory die | Scott E. Smith | 2018-12-18 |
| RE45248 | Cascaded connection matrices in a distributed cross-connection system | Miriam Qunell, Jean-Michel Caia | 2014-11-18 |
| 8705218 | Input buffer protection | — | 2014-04-22 |
| 8508278 | Apparatus and method for external to internal clock generation | Tyler Gomm, Scott E. Smith | 2013-08-13 |
| 8169759 | Circuit and methods to protect input buffer | — | 2012-05-01 |
| 7936199 | Apparatus and method for external to internal clock generation | Tyler Gomm, Scott E. Smith | 2011-05-03 |
| 7602777 | Cascaded connection matrices in a distributed cross-connection system | Miriam Qunell, Jean-Michel Cala | 2009-10-13 |
| 7583664 | Techniques for transmitting and receiving traffic over advanced switching compatible switch fabrics | Miriam Qunell, Jason Garratt, Kevin Bradley Citterelle, Jeff Fedders, Michael Kauschke +3 more | 2009-09-01 |