| 5579504 |
Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions |
G. Michael Uhler, W. Hugh Durdan |
1996-11-26 |
| 5276852 |
Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions |
Douglas E. Sanders |
1994-01-04 |
| 5233616 |
Write-back cache with ECC protection |
— |
1993-08-03 |
| 5226150 |
Apparatus for suppressing an error report from an address for which an error has already been reported |
Linda Chao, Douglas E. Sanders |
1993-07-06 |
| 5193163 |
Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol |
Douglas E. Sanders |
1993-03-09 |
| 5155843 |
Error transition mode for multi-processor system |
Rebecca L. Stamm, R. Iris Bahar, Linda Chao, Derrick R. Meyer, Douglas E. Sanders +3 more |
1992-10-13 |