MK

Makarand Ramkrishna Kulkarni

TI Texas Instruments: 15 patents #889 of 12,488Top 8%
SP Saankhya Labs Pvt.: 2 patents #10 of 32Top 35%
EB Ebay: 1 patents #1,423 of 2,086Top 70%
📍 Dallas, TX: #378 of 7,543 inventorsTop 6%
🗺 Texas: #7,815 of 125,132 inventorsTop 7%
Overall (All Time): #243,971 of 4,157,543Top 6%
18
Patents All Time

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDate
12406915 Plated metal layer in power packages Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Yiqi Tang, Rajen Manicon Murugan, Liang Wan 2025-09-02
12322856 Antenna in package having antenna on package substrate Yiqi Tang, Liang Wan, Rajen Manicon Murugan 2025-06-03
12211800 Semiconductor package with shunt and patterned metal trace Yiqi Tang, Rajen Manicon Murugan, Liang Wan, Jie Chen, Steven Kummerl 2025-01-28
12015019 Stacked die multichip module package Jonathan Almeria Noquil 2024-06-18
11963042 System and method for offloading traffic from a cellular network to a broadcast network Arindam Chakraborty, Anindya Saha, Gururaj Padaki, Parag Naik, Preetham Uthaiah 2024-04-16
11955479 Packaged semiconductor device Yiqi Tang, Rajen Manicon Murugan 2024-04-09
11784114 Plated metal layer in power packages Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Yiqi Tang, Rajen Manicon Murugan, Liang Wan 2023-10-10
11430720 Recess lead for a surface mount package Naweed Anjum, Michael G. Amaro 2022-08-30
11259209 System and method for dynamically switching transmission of data from cellular to unidirectional point-to-multipoint network Parag Naik, Arindam Chakraborty, Anindya Saha, Vishwakumara Kayargadde, Mark A. AITKEN 2022-02-22
11217460 Multiple underfills for flip chip packages Tae Hee Kim 2022-01-04
11160163 Electronic substrate having differential coaxial vias Snehamay Sinha, Tapobrata Bandyopadhyay 2021-10-26
11081472 Stacked die multichip module package Jonathan Almeria Noquil 2021-08-03
10475786 Packaged semiconductor device Yiqi Tang, Rajen Manicon Murugan 2019-11-12
8614143 Simultaneous via and trench patterning using different etch rates Deepak A. Ramappa 2013-12-24
8379433 3T DRAM cell with added capacitance on storage node Theodore W. Houston, James (Hsu-Hsuan) Lan 2013-02-19
8015239 Method and system to reduce false positives within an automated software-testing environment Anoop Sharma, I-Chin Chen, Nadir Hussain, Corey Innis 2011-09-06
7855090 In line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same Andrew Marshall 2010-12-21
7786475 In-line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same Andrew Marshall 2010-08-31