Issued Patents All Time
Showing 1–25 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12141071 | Performance and reliability of processor store operation data transfers | Shakti Kapoor, Nelson Wu | 2024-11-12 |
| 12130749 | Validation of store coherence relative to page translation invalidation | Shakti Kapoor, Nelson Wu | 2024-10-29 |
| 12118355 | Cache coherence validation using delayed fulfillment of L2 requests | Shakti Kapoor, Nelson Wu | 2024-10-15 |
| 11620235 | Validation of store coherence relative to page translation invalidation | Shakti Kapoor, Nelson Wu | 2023-04-04 |
| 11163661 | Test case generation for a hardware state space | Madhusudan Kadiyala, Narasimha R. Adiga | 2021-11-02 |
| 11094391 | List insertion in test segments with non-naturally aligned data boundaries | Shakti Kapoor, Nelson Wu | 2021-08-17 |
| 11061821 | Method, system, and apparatus for stress testing memory translation tables | Shakti Kapoor, Nelson Wu | 2021-07-13 |
| 10877864 | Controlling segment layout in a stress test for a processor memory with a link stack | Shakti Kapoor | 2020-12-29 |
| 10831620 | Core pairing in multicore systems | Prasanna Jayaraman, Rahul M. Rao | 2020-11-10 |
| 10748637 | System and method for testing processor errors | Nelson Wu, Shakti Kapoor, Nandhini Rajaiah | 2020-08-18 |
| 10713179 | Efficiently generating effective address translations for memory management test cases | Shakti Kapoor | 2020-07-14 |
| 10540249 | Stress testing a processor memory with a link stack | Shakti Kapoor | 2020-01-21 |
| 10521355 | Method, system, and apparatus for stress testing memory translation tables | Shakti Kapoor, Nelson Wu | 2019-12-31 |
| 10489261 | Efficient testing of direct memory address translation | Shakti Kapoor, Nelson Wu | 2019-11-26 |
| 10489259 | Replicating test case data into a cache with non-naturally aligned data boundaries | Shakti Kapoor | 2019-11-26 |
| 10481991 | Efficient testing of direct memory address translation | Shakti Kapoor, Nelson Wu | 2019-11-19 |
| 10438682 | List insertion in test segments with non-naturally aligned data boundaries | Shakti Kapoor, Nelson Wu | 2019-10-08 |
| 10346314 | Efficiently generating effective address translations for memory management test cases | Shakti Kapoor | 2019-07-09 |
| 10318667 | Test case generation | Madhusudan Kadiyala, John Paul | 2019-06-11 |
| 10318456 | Validation of correctness of interrupt triggers and delivery | Shakti Kapoor, Brenton Yiu, Siva Sundar A | 2019-06-11 |
| 10261917 | Identifying stale entries in address translation cache | Vinod Bussa, Shakti Kapoor | 2019-04-16 |
| 10261878 | Stress testing a processor memory with a link stack | Shakti Kapoor | 2019-04-16 |
| 10241880 | Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems | Shakti Kapoor | 2019-03-26 |
| 10223225 | Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries | Shakti Kapoor | 2019-03-05 |
| 10169185 | Efficient testing of direct memory address translation | Shakti Kapoor, Nelson Wu | 2019-01-01 |