Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6958936 | Erase inhibit in non-volatile memories | Raul-Adrian Cernea | 2005-10-25 |
| 6944068 | Method and system for programming and inhibiting multi-level, non-volatile memory cells | Khanh Nguyen, Feng Pan, Long Pham, Alexander Kwok-Tung Mak | 2005-09-13 |
| 6888752 | Method of reducing disturbs in non-volatile memory | John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang | 2005-05-03 |
| 6870768 | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells | Raul-Adrian Cernea, Yan Li, Jian Chen, Yupin Fong | 2005-03-22 |
| 6839281 | Read and erase verify methods and circuits suitable for low voltage non-volatile memories | Jian Chen | 2005-01-04 |
| 6807095 | Multi-state nonvolatile memory capable of reducing effects of coupling between storage elements | Jian Chen, Tomoharu Tanaka, Yupin Fong | 2004-10-19 |
| 6781877 | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells | Raul-Adrian Cernea, Yan Li, Jian Chen, Yupin Fong | 2004-08-24 |
| 6717851 | Method of reducing disturbs in non-volatile memory | John S. Mangan, Daniel C. Guterman, George Samachisa, Brian Murphy, Chi-Ming Wang | 2004-04-06 |
| 6696880 | High voltage switch suitable for non-volatile memories | Feng Pan | 2004-02-24 |
| 6522580 | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states | Jian Chen, Tomoharu Tanaka, Yupin Fong | 2003-02-18 |
| 6396757 | Multiple output current mirror with improved accuracy | Sharon Huynh | 2002-05-28 |
| 6285615 | Multiple output current mirror with improved accuracy | Sharon Huynh | 2001-09-04 |
| 6282130 | EEPROM memory chip with multiple use pinouts | Raul-Adrian Cernea, Sanjay Mehrotra | 2001-08-28 |
| 5994937 | Temperature and power supply adjusted address transition detector | Takahiko Hara, Yohji Watanabe | 1999-11-30 |
| 5243700 | Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port | Robert E. Larsen, Joseph H. Salmon, Terry L. Kendall | 1993-09-07 |
| 5077738 | Test mode enable scheme for memory | Robert E. Larsen, Joseph H. Salmon | 1991-12-31 |
| 5057715 | CMOS output circuit using a low threshold device | Robert E. Larsen, Joseph H. Salmon | 1991-10-15 |