KD

Keith Dennison

CS Cadence Design Systems: 12 patents #85 of 2,263Top 4%
Overall (All Time): #417,848 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9589085 Systems and methods for viewing analog simulation check violations in an electronic design automation framework Donald J. O'Riordan, Vuk Borich 2017-03-07
9501598 System and method for assertion publication and re-use Donald J. O'Riordan, Vuk Borich 2016-11-22
9286420 Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation Prakash Krishnan, Jeremiah Cessna, Akshat Shah 2016-03-15
9223925 Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness Prakash Krishnan, Michael McSherry, David White, Ed Fischer, Bruce Yanagida 2015-12-29
9047424 System and method for analog verification IP authoring and storage Mark D. Baker, Donald J. O'Riordan 2015-06-02
8769456 Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation Prakash Krishnan, Jeremiah Cessna, Akshat Shah 2014-07-01
8694950 Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Prakash Gopalakrishnan +1 more 2014-04-08
8694933 Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness Prakash Gopalakrishnan, Michael McSherry, David White, Ed Fischer, Bruce Yanagida 2014-04-08
8612921 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy Prakash Gopalakrishnan, Rongchang Yan, Akshat Shah, David N. Dixon 2013-12-17
8584072 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy Prakash Gopalakrishnan, Rongchang Yan, Akshat Shah, David N. Dixon 2013-11-12
8261228 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy Prakash Gopalakrishnan, Rongchang Yan, Akshat Shah, David N. Dixon 2012-09-04
7277804 Method and system for performing effective resistance calculation for a network of resistors Ian Gebbie, Ian Campbell Dennison, Zsolt Haag 2007-10-02