Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11508806 | Low leakage ESD MOSFET | Eric Braun | 2022-11-22 |
| 11069777 | Manufacturing method of self-aligned DMOS body pickup | Ji-Hyoung Yoo, Haifeng Yang, Deming Xiao | 2021-07-20 |
| 10665712 | LDMOS device with a field plate contact metal layer with a sub-maximum size | Eric Braun, Jeesung Jung | 2020-05-26 |
| 10090409 | Method for fabricating LDMOS with self-aligned body | Deming Xiao, Zeqiang Yao, Ji-Hyoung Yoo, Jeesung Jung | 2018-10-02 |
| 9941171 | Method for fabricating LDMOS with reduced source region | Ji-Hyoung Yoo, Eric Braun | 2018-04-10 |
| 9893170 | Manufacturing method of selectively etched DMOS body pickup | Ji-Hyoung Yoo, Jeesung Jung | 2018-02-13 |
| 9893146 | Lateral DMOS and the method for forming thereof | Eric Braun, Jeesung Jung, Ji-Hyoung Yoo | 2018-02-13 |
| 9502251 | Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process | Jeesung Jung, Ji-Hyoung Yoo, Eric Braun | 2016-11-22 |
| 9450052 | EEPROM memory cell with a coupler region and method of making the same | Albert Bergemont, Eric Braun | 2016-09-20 |
| 9087774 | LDMOS device with short channel and associated fabrication method | Jeesung Jung, Ji-Hyoung Yoo | 2015-07-21 |
| 9041102 | Power transistor and associated method for manufacturing | — | 2015-05-26 |
| 8987818 | Integrated MOS power transistor with thin gate oxide and low gate charge | Vishnu Khemka | 2015-03-24 |
| 8946851 | Integrated MOS power transistor with thin gate oxide and low gate charge | Vishnu Khemka | 2015-02-03 |
| 6362064 | Elimination of walkout in high voltage trench isolated devices | Rashid Bashir, Wipawan Yindeepol | 2002-03-26 |
| 5811315 | Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure | Wipawan Yindeepol, Rashid Bashir, Kevin Brown, Joseph Anthony DeSantis | 1998-09-22 |