JS

Jayesh V. Sheth

UN Unisys: 10 patents #92 of 2,015Top 5%
BU Burroughs: 7 patents #20 of 604Top 4%
Overall (All Time): #280,550 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
5809533 Dual bus system with multiple processors having data coherency maintenance Dan T. Tran, Paul B. Ricci, Theodore C. White, Richard A. Cowgill 1998-09-15
5737756 Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue Theodore C. White 1998-04-07
5696937 Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses Theodore C. White 1997-12-09
5666515 Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address Theodore C. White, Kha Nguyen, Dan T. Tran 1997-09-09
5519883 Interbus interface module Theodore C. White, Chung W. Wong, Kha Nguyen, Craig W. Harris 1996-05-21
5511224 Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories Dan T. Tran, Paul B. Ricci, Theodore C. White, Richard A. Cowgill 1996-04-23
5386517 Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds Craig W. Harris, Theodore C. White, Kha Nguyen, Chung W. Wong, Richard A. Cowgill 1995-01-31
5349620 Timer access control apparatus Theodore C. White, Kha Nguyen 1994-09-20
5293621 Varying wait interval retry apparatus and method for preventing bus lockout Theodore C. White, Paul B. Ricci, Dan T. Tran 1994-03-08
5293496 Inhibit write apparatus and method for preventing bus lockout Theodore C. White, Dan T. Tran, Paul B. Ricci 1994-03-08
4644463 System for regulating data transfer operations Glenn T. Hotchkin, David Jon Mortensen 1987-02-17
4616337 Automatic read system for peripheral-controller — 1986-10-07
4613954 Block counter system to monitor data transfers — 1986-09-23
4607348 Transfer rate control system from tape peripheral to buffer memory of peripheral controller — 1986-08-19
4602331 Magnetic tape-data link processor providing automatic data transfer — 1986-07-22
4542457 Burst mode data block transfer system David Jon Mortensen 1985-09-17
4534013 Automatic write system for peripheral-controller — 1985-08-06