Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7541237 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Jack Yuan | 2009-06-02 |
| 7288455 | Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors | Jack Yuan | 2007-10-30 |
| 6953964 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Jack Yuan | 2005-10-11 |
| 6723604 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Jack Yuan | 2004-04-20 |
| 6512263 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Jack Yuan | 2003-01-28 |
| 6429132 | Combination CMP-etch method for forming a thin planar layer over the surface of a device | Rong-Fu Hsu | 2002-08-06 |
| 6297170 | Sacrificial multilayer anti-reflective coating for mos gate formation | Calvin T. Gabriel, Satyendra Sethi | 2001-10-02 |
| 6277748 | Method for manufacturing a planar reflective light valve backplane | Rong-Fu Hsu | 2001-08-21 |
| 6252999 | Planar reflective light valve backplane | Rong-Fu Hsu | 2001-06-26 |
| 6133635 | Process for making self-aligned conductive via structures | Subhas Bothra | 2000-10-17 |
| 6110818 | Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof | — | 2000-08-29 |
| 5776821 | Method for forming a reduced width gate electrode | Satyendra Sethi, Calvin T. Gabriel | 1998-07-07 |
| 5395796 | Etch stop layer using polymers for integrated circuits | Subhash Gupta | 1995-03-07 |
| 5198298 | Etch stop layer using polymers | Subhash Gupta | 1993-03-30 |
| 5136361 | Stratified interconnect structure for integrated circuits | Donald L. Wollesen, Craig S. Sander | 1992-08-04 |
| 5116778 | Dopant sources for CMOS device | Steven C. Avanzino, Balaji Swaminathan | 1992-05-26 |
| 5091326 | EPROM element employing self-aligning process | — | 1992-02-25 |
| 5081516 | Self-aligned, planarized contacts for semiconductor devices | — | 1992-01-14 |
| 5057902 | Self-aligned semiconductor devices | — | 1991-10-15 |
| 5055427 | Process of forming self-aligned interconnects for semiconductor devices | — | 1991-10-08 |
| 5028555 | Self-aligned semiconductor devices | — | 1991-07-02 |
| 4977108 | Method of making self-aligned, planarized contacts for semiconductor devices | — | 1990-12-11 |
| 4974055 | Self-aligned interconnects for semiconductor devices | — | 1990-11-27 |
| 4964143 | EPROM element employing self-aligning process | — | 1990-10-16 |
| 4962064 | Method of planarization of topologies in integrated circuit structures | Craig S. Sander, Steven C. Avanzino, Subhash Gupta | 1990-10-09 |