Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8448107 | Method for piecewise hierarchical sequential verification | Nathan Francis Sheeley, Mark H. Nodine, Nicolas X. Pena, Patrick Peters, Adrian Isles | 2013-05-21 |
| 8429580 | Method for preparing for and formally verifying a modified integrated circuit design | Raymond Cheung Yeung, Mark H. Nodine | 2013-04-23 |