Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679890 | Junction-less insulated gate current limiter device | Tirthajyoti Sarkar, Adrian Mikolajczak, Ashok Challa | 2017-06-13 |
| 8592277 | Method of forming low resistance gate for power MOSFET applications | Sreevatsa Sreekantham, Fred Session, James Kent Naylor | 2013-11-26 |
| 8536042 | Method of forming a topside contact to a backside terminal of a semiconductor device | John T. Andrews, Hamza Yilmaz, Bruce D. Marchant | 2013-09-17 |
| 8072027 | 3D channel architecture for semiconductor devices | Suku Kim, Dan Calafut, Dan Kinzer, Steven Sapp, Ashok Challa +2 more | 2011-12-06 |
| 8058732 | Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same | Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu +2 more | 2011-11-15 |
| 8003522 | Method for forming trenches with wide upper portion and narrow lower portion | Hui-Chi Chen, Stacy W. Hall, Briant Harward, Hossein Paravi | 2011-08-23 |
| 7989884 | Structure for making a top-side contact to a substrate | Chun-Tai Wu | 2011-08-02 |
| 7884390 | Structure and method of forming a topside contact to a backside terminal of a semiconductor device | John T. Andrews, Hamza Yilmaz, Bruce D. Marchant | 2011-02-08 |
| 7807536 | Low resistance gate for power MOSFET applications and method of manufacture | Sreevatsa Sreekantham, Fred Session, Kent Naylor | 2010-10-05 |
| 7482645 | Method and structure for making a top-side contact to a substrate | Chun-Tai Wu | 2009-01-27 |