Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8549217 | Spacing periodic commands to a volatile memory for increased performance and decreased collision | Ronald E. Freking, Ryan Scott Haraden, Joseph A. Kirscht | 2013-10-01 |
| 8352786 | Compressed replay buffer | Ryan Scott Haraden, Joseph A. Kirscht, Elizabeth A. McGlone | 2013-01-08 |
| 8205138 | Memory controller for reducing time to initialize main memory | Joseph A. Kirscht, Elizabeth A. McGlone | 2012-06-19 |
| 8127087 | Memory controller for improved read port selection in a memory mirrored system | Joseph A. Kirscht, Elizabeth A. McGlone, Jeb A. Shookman | 2012-02-28 |
| 8082396 | Selecting a command to send to memory | Philip Hillier, Joseph A. Kirscht, Brian T. Vanderpool | 2011-12-20 |
| 8028128 | Method for increasing cache directory associativity classes in a system with a register space memory | Duane A. Averill, Joseph A. Kirscht, David A. Shedivy | 2011-09-27 |
| 7925857 | Method for increasing cache directory associativity classes via efficient tag bit reclaimation | Duane A. Averill, Joseph A. Kirscht, David A. Shedivy | 2011-04-12 |
| 7650259 | Method for tuning chipset parameters to achieve optimal performance under varying workload types | Joseph A. Kirscht, David A. Shedivy, Brian T. Vanderpool | 2010-01-19 |
| 7010654 | Methods and systems for re-ordering commands to access memory | Joseph A. Kirscht, James Anthony Marcella, Brian T. Vanderpool | 2006-03-07 |
| 6963516 | Dynamic optimization of latency and bandwidth on DRAM interfaces | John Michael Borkenhagen, Joseph A. Kirscht, James Anthony Marcella, David A. Shedivy | 2005-11-08 |
| 6895482 | Reordering and flushing commands in a computer memory subsystem | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2005-05-17 |
| 6628662 | Method and system for multilevel arbitration in a non-blocking crossbar switch | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2003-09-30 |
| 6523080 | Shared bus non-sequential data ordering method and apparatus | Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David J. Krolak, James Anthony Marcella +1 more | 2003-02-18 |
| 6513091 | Data routing using status-response signals | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2003-01-28 |
| 6505306 | Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2003-01-07 |
| 6188627 | Method and system for improving DRAM subsystem performance using burst refresh control | Robert Allen Drehmel, Kent Harold Haselhorst, William Paul Hovis, James Anthony Marcella | 2001-02-13 |
| 5748919 | Shared bus non-sequential data ordering method and apparatus | Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David J. Krolak, James Anthony Marcella +1 more | 1998-05-05 |