Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10599566 | Multi-mode cache invalidation | Ramasamy Adaikkalavan, Rajesh Kumar | 2020-03-24 |
| 10559352 | Bitline-driven sense amplifier clocking scheme | Manish Garg, Rahul K. Nadkarni, Rajesh Kumar, Michael ThaiThanh Phan | 2020-02-11 |
| 9666269 | Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods | Manish Garg, Joshua Puckett, Rahul K. Nadkarni | 2017-05-30 |
| 9129706 | Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers | David Paul Hoff, Manish Garg | 2015-09-08 |
| 9093125 | Low voltage write speed bitcell | Joshua Puckett, Manish Garg | 2015-07-28 |