Issued Patents All Time
Showing 25 most recent of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386665 | Method for managing resources, computing device and computer-readable storage medium | Long Chen, Haichuan Wang | 2025-08-12 |
| 12236277 | Apparatus and method for secondary offloads in graphics processing unit | Haichuan Wang, Song Zhao, ChengPing Luo, Zhou Hong | 2025-02-25 |
| 12197955 | Heterogeneous scheduling for sequential compute DAG | Shouwen Lai | 2025-01-14 |
| 11809221 | Artificial intelligence chip and data operation method | Zhou Hong, Qin Zheng, ChengPing Luo, Song Zhao, XiangLiang Yu | 2023-11-07 |
| 11748077 | Apparatus and method and computer program product for compiling code adapted for secondary offloads in graphics processing unit | Haichuan Wang, Song Zhao, ChengPing Luo, Zhou Hong | 2023-09-05 |
| 11663044 | Apparatus and method for secondary offloads in graphics processing unit | Haichuan Wang, Song Zhao, ChengPing Luo, Zhou Hong | 2023-05-30 |
| 10658335 | Heterogenous 3D chip stack for a mobile processor | Shiqun Gu, Yu Lin, Jinghua Zhu | 2020-05-19 |
| 10558460 | General purpose register allocation in streaming processor | Yun Du, Liang Han, Lin Chen, Chihong Zhang, Hongjiang Shang +5 more | 2020-02-11 |
| 10388060 | System and method for multi-view rendering | — | 2019-08-20 |
| 10241799 | Out-of-order command execution with sliding windows to maintain completion statuses | Alexei V. Bourd | 2019-03-26 |
| 9852536 | High order filtering in a graphics processing unit | Liang Li, Yunshan Kong, Javier Ignacio Girado | 2017-12-26 |
| 9799089 | Per-shader preamble for graphics processing | Lin Chen, Yun Du, Andrew Evan Gruber, Chun Yu, David Rigel Garcia Garcia | 2017-10-24 |
| 9697580 | Dynamic pipeline for graphics processing | Liang Li, Andrew Evan Gruber, Zhenyu Qi, Gregory Pitarys, Scott William Nolan | 2017-07-04 |
| 9633411 | Load scheme for shared register in GPU | Yun Du, Andrew Evan Gruber, Lin Chen, Chun Yu | 2017-04-25 |
| 9454841 | High order filtering in a graphics processing unit | Liang Li, Yunshan Kong, Javier Ignacio Girado | 2016-09-27 |
| 9123168 | Output ordering of domain coordinates for tessellation | Chunhui Mei, Nariman Moezzi Madani, Vineet Goel, Usame Ceylan | 2015-09-01 |
| 8884972 | Graphics processor with arithmetic and elementary function units | Yun Du, Chun Yu, Alexei V. Bourd | 2014-11-11 |
| 8869147 | Multi-threaded processor with deferred thread output control | Yun Du, Chun Yu | 2014-10-21 |
| 8854383 | Pixel value compaction for graphics processing | Ming-Chang Tsai | 2014-10-07 |
| 8832417 | Program flow control for multiple divergent SIMD threads using a minimum resume counter | Lin Chen, David Rigel Garcia Garcia, Andrew Evan Gruber | 2014-09-09 |
| 8773459 | 3-D clipping in a graphics processing unit | Chun Yu, Lingjun Chen, Yun Du | 2014-07-08 |
| 8766996 | Unified virtual addressed register file | Yun Du, Chun Yu, De Dzwo Hsu | 2014-07-01 |
| 8766995 | Graphics system with configurable caches | Chun Yu, Yun Du | 2014-07-01 |
| 8760457 | Data access tool for programmable graphics hardware | Alexei V. Bourd, Lin Chen | 2014-06-24 |
| 8643644 | Multi-stage tessellation for graphics rendering | Jian Wei, Ning Bi, Chehui Wu | 2014-02-04 |