Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10355975 | Latency guaranteed network on chip | Paul Michael Sebexen, Thomas Rex Sohmers, Edmond A. Cote, Piyush Shrinivas Kasat | 2019-07-16 |
| 9142060 | Computation reduced tessellation | Jian Mao, Vineet Goel | 2015-09-22 |
| 9123168 | Output ordering of domain coordinates for tessellation | Chunhui Mei, Vineet Goel, Usame Ceylan, Guofang Jiao | 2015-09-01 |
| 9082204 | Storage structures for stitching primitives in graphics processing | Vineet Goel, Jian Mao | 2015-07-14 |