Issued Patents All Time
Showing 25 most recent of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12422985 | Write quality in memory systems | Nitul Gohain, David Aaron Palmer | 2025-09-23 |
| 12411775 | Dual address encoding for logical-to-physical mapping | Jonathan S. Parry | 2025-09-09 |
| 12386543 | Opportunistic storage of non-write-boosted data in write booster cache memory | Jonathan S. Parry, Reshmi Basu | 2025-08-12 |
| 12386562 | Dynamic status registers array | Reshmi Basu | 2025-08-12 |
| 12379991 | Error detection event mechanism | — | 2025-08-05 |
| 12353325 | Host logical-to-physical information refresh | — | 2025-07-08 |
| 12353723 | Low-power boot-up for memory systems | Reshmi Basu, Jonathan S. Parry, David Aaron Palmer, Luca Porzio, Stephen Hanna | 2025-07-08 |
| 12354638 | Signaling memory zone ranking information | — | 2025-07-08 |
| 12346582 | Techniques for memory system rebuild | — | 2025-07-01 |
| 12248705 | Dynamic memory address write policy translation based on performance needs | Jonathan S. Parry | 2025-03-11 |
| 12230232 | Configurable types of write operations | — | 2025-02-18 |
| 12223184 | Distributed power up for a memory system | — | 2025-02-11 |
| 12216572 | Atomic write operations | — | 2025-02-04 |
| 12189522 | Techniques for suspend operations | Justin Bates, Ryan Hrinya, Fulvio Rori, Chiara Cerafogli, Carmine Miccoli | 2025-01-07 |
| 12182015 | Weighted valid address count for garbage collection | — | 2024-12-31 |
| 12182407 | Monitoring flash memory erase progress using erase credits | Fulvio Rori, Jung Sheng Hoei | 2024-12-31 |
| 12159041 | Techniques for failure management in memory systems | — | 2024-12-03 |
| 12132832 | Secure key update for replay protected memory blocks | Gaspare Giglio, Patrick Miesen, Jonathan S. Parry | 2024-10-29 |
| 12124366 | Smart factory reset procedure | — | 2024-10-22 |
| 12124322 | Access operation status signaling for memory systems | Qing Liang, Jonathan S. Parry, Deping He | 2024-10-22 |
| 12105959 | Suspending operations of a memory system | David Aaron Palmer, Fulvio Rori | 2024-10-01 |
| 12099748 | NAND temperature-aware operations | Chiara Cerafogli, Fulvio Rori, Jonathan W. Oh | 2024-09-24 |
| 12099449 | Using a flag to indicate whether a mapping entry points to sequentially stored data | Jonathan S. Parry | 2024-09-24 |
| 12050773 | Completion flag for memory operations | Jonathan S. Parry | 2024-07-30 |
| 12045495 | Read latency and suspend modes | — | 2024-07-23 |