Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11669303 | Multiply-accumulate circuit | — | 2023-06-06 |
| 11593455 | Scalable matrix computation circuit | — | 2023-02-28 |
| 11593456 | Resistive matrix computation circuit | — | 2023-02-28 |
| 10916298 | Dynamic power reduction in SRAM | — | 2021-02-09 |
| 10896723 | Signal communication circuit implementing receiver and transmitter circuits | — | 2021-01-19 |
| 10867094 | Adjustable integrated circuits and methods for designing the same | — | 2020-12-15 |
| 10832762 | Static power reduction in SRAM | — | 2020-11-10 |
| 10819362 | High speed analog to digital converter | — | 2020-10-27 |
| 10503184 | Dynamic adjustment of operating conditions of integrated circuits | — | 2019-12-10 |
| 9960771 | Hum generation using representative circuitry | Shaishav Desai | 2018-05-01 |
| 9440857 | Process for high-yield production of graphene via detonation of carbon-containing material | Christopher Sorensen, Arjun Nepal | 2016-09-13 |
| 9385715 | Multi-threshold flash NCL logic circuitry with flash reset | — | 2016-07-05 |
| 9361950 | Semiconductor device with reduced leakage current and method for manufacture of the same | — | 2016-06-07 |
| 9257984 | Multi-threshold circuitry based on silicon-on-insulator technology | Roger Carpenter | 2016-02-09 |
| 9203406 | Implementation method for fast NCL data path | — | 2015-12-01 |
| 9024655 | Multi-threshold flash NCL circuitry | — | 2015-05-05 |
| 8981812 | Self-ready flash null convention logic | Richard Shaw Terrill | 2015-03-17 |
| 8212026 | Process for the preparation of ivabradine hydrochloride and polymorph thereof | Satyendra Singh, Lalit Wadhwa | 2012-07-03 |
| 7120915 | Thread switch circuit design and signal encoding for vertical threading | Joseph I. Chamdani, Renu Raman, Rabin Sugumar | 2006-10-10 |
| 7109767 | Generating different delay ratios for a strobe delay | Brian Amick, Aparna Ramachandran, Dong J. Yoon, Tri Tran, Claude Gauthier | 2006-09-19 |
| 7107475 | Digital delay locked loop with extended phase capture range | Brian Amick, Dong J. Yoon, Tri Tran, Aparna Ramachandran, Claude Gauthier | 2006-09-12 |
| 6747485 | Sense amplifier type input receiver with improved clk to Q | Samudyatha Suryanarayana | 2004-06-08 |
| 6707721 | Low power memory design with asymmetric bit line driver | Aparna Ramachandran, Miao Rao, Shree Kant | 2004-03-16 |
| 6578168 | Method for operating a boundary scan cell design for high performance I/O cells | Ishwardutt Parulkar, Sridhar Narayanan, Jaya Prakash Samala | 2003-06-10 |
| 6570409 | Current steering logic circuits | Priya Ananthanarayanan | 2003-05-27 |