GG

Gary K. Giust

Lsi Logic: 14 patents #102 of 1,957Top 6%
Cypress Semiconductor: 1 patents #1,072 of 1,852Top 60%
Overall (All Time): #205,400 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11592480 Method and apparatus for analyzing phase noise in a signal from an electronic device 2023-02-28
11231459 Method and apparatus for analyzing phase noise in a signal from an electronic device 2022-01-25
10802074 Method and apparatus for analyzing phase noise in a signal from an electronic device 2020-10-13
9003549 Analysis of an analog property of a signal 2015-04-07
8891602 Analyzing jitter with noise from the measurement environment 2014-11-18
8473233 Analyzing jitter in a clock timing signal 2013-06-25
7388440 Circuit and method to speed up PLL lock-time and prohibit frequency runaway Chwei-Po Chew, Sung-Ki Min 2008-06-17
6977400 Silicon germanium CMOS channel Helmut Puchner 2005-12-20
6770947 Laser-breakable fuse link with alignment and break point promotion structures Ruggero Castagnetti, Yauh-Ching Liu, Shiva Ramesh 2004-08-03
6566730 Laser-breakable fuse link with alignment and break point promotion structures Ruggero Castagnetti, Yauh-Ching Liu, Shiva Ramesh 2003-05-20
6544854 Silicon germanium CMOS channel Helmut Puchner 2003-04-08
6455363 System to improve ser immunity and punchthrough Helmut Puchner, Weiran Kong 2002-09-24
6442061 Single channel four transistor SRAM Weiran Kong, Ramnath Venkatraman, Yauh-Ching Liu, Franklin Duan, Ruggero Castagnetti +3 more 2002-08-27
6413848 Self-aligned fuse structure and method with dual-thickness dielectric Ruggero Castagnetti, Yauh-Ching Liu, Subramanian Ramesh 2002-07-02
6259146 Self-aligned fuse structure and method with heat sink Ruggero Castagnetti, Yauh-Ching Liu, Subramanian Ramesh 2001-07-10
6218276 Silicide encapsulation of polysilicon gate and interconnect Yauh-Ching Liu, Ruggero Castagnetti, Subramanian Ramesh 2001-04-17
6162714 Method of forming thin polygates for sub quarter micron CMOS process Ruggero Castagnetti, Yauh-Ching Liu, Subramanian Ramesh 2000-12-19
6090651 Depletion free polysilicon gate electrodes Helmut Puchner, Sheldon Aronowitz 2000-07-18
6061264 Self-aligned fuse structure and method with anti-reflective coating Ruggero Castagnetti, Yauh-Ching Liu, Subramanian Ramesh 2000-05-09
6037233 Metal-encapsulated polysilicon gate and interconnect Yauh-Ching Liu, Ruggero Castagnetti, Subramanian Ramesh 2000-03-14
5953614 Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step Yauh-Ching Liu, Ruggero Castagnetti, Subramanian Ramesh 1999-09-14