Issued Patents All Time
Showing 25 most recent of 379 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11226840 | Neural network unit that interrupts processing core upon condition | Terry Parks | 2022-01-18 |
| 11221872 | Neural network unit that interrupts processing core upon condition | Terry Parks | 2022-01-11 |
| 11216720 | Neural network unit that manages power consumption based on memory accesses per period | — | 2022-01-04 |
| 11061853 | Processor with memory controller including dynamically programmable functional unit | Rodney E. Hooker, Terry Parks, Douglas R. Reed | 2021-07-13 |
| 11029949 | Neural network unit | Douglas R. Reed, Kim C. Houck, Parviz Palangpour | 2021-06-08 |
| 10776690 | Neural network unit with plurality of selectable output functions | Terry Parks | 2020-09-15 |
| 10725934 | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode | Terry Parks, Douglas R. Reed | 2020-07-28 |
| 10671564 | Neural network unit that performs convolutions using collective shift register among array of neural processing units | Terry Parks, Kyle T. O'Brien | 2020-06-02 |
| 10664751 | Processor with memory array operable as either cache memory or neural network unit memory | Douglas R. Reed | 2020-05-26 |
| 10642617 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | Rodney E. Hooker, Terry Parks, Douglas R. Reed | 2020-05-05 |
| 10635453 | Dynamic reconfiguration of multi-core processor | Terry Parks, Darius D. Gaskins | 2020-04-28 |
| 10586148 | Neural network unit with re-shapeable memory | Kim C. Houck, Parviz Palangpour | 2020-03-10 |
| 10585848 | Processor with hybrid coprocessor/execution unit neural network unit | Terry Parks | 2020-03-10 |
| 10565492 | Neural network unit with segmentable array width rotator | Kim C. Houck, Parviz Palangpour | 2020-02-18 |
| 10565494 | Neural network unit with segmentable array width rotator | Kim C. Houck, Parviz Palangpour | 2020-02-18 |
| 10552370 | Neural network unit with output buffer feedback for performing recurrent neural network computations | Terry Parks, Kyle T. O'Brien | 2020-02-04 |
| 10515302 | Neural network unit with mixed data and weight size computation capability | Kim C. Houck | 2019-12-24 |
| 10509765 | Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value | Terry Parks | 2019-12-17 |
| 10474627 | Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory | Terry Parks | 2019-11-12 |
| 10474628 | Processor with variable rate execution unit | Terry Parks | 2019-11-12 |
| 10438115 | Neural network unit with memory layout to perform efficient 3-dimensional convolutions | Kim C. Houck | 2019-10-08 |
| 10430706 | Processor with memory array operable as either last level cache slice or neural network unit memory | Douglas R. Reed | 2019-10-01 |
| 10423216 | Asymmetric multi-core processor with native switching mechanism | Rodney E. Hooker, Terry Parks | 2019-09-24 |
| 10423876 | Processor with memory array operable as either victim cache or neural network unit memory | Douglas R. Reed | 2019-09-24 |
| 10417560 | Neural network unit that performs efficient 3-dimensional convolutions | Kim C. Houck | 2019-09-17 |