| 6378061 |
Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit |
Adrian Carbine, Glenn J. Hinton |
2002-04-23 |
| 5459845 |
Instruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completed |
Truong-Thao Nguyen |
1995-10-17 |
| 5454089 |
Branch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decoding |
Truong-Thao Nguyen |
1995-09-26 |
| 5428811 |
Interface between a register file which arbitrates between a number of single cycle and multiple cycle functional units |
Glenn J. Hinton, Randy Steck |
1995-06-27 |
| 5313605 |
High bandwith output hierarchical memory store including a cache, fetch buffer and ROM |
Scott Huck, Sunil Shenoy |
1994-05-17 |
| H1291 |
Microprocessor in which multiple instructions are executed in one clock |
Glenn J. Hinton |
1994-02-01 |
| 5222244 |
Method of modifying a microinstruction with operands specified by an instruction held in an alias register |
Adrian Carbine |
1993-06-22 |
| 5185872 |
System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy |
James M. Arnold, Glenn J. Hinton |
1993-02-09 |
| 5023844 |
Six-way access ported RAM array cell |
James M. Arnold, Glenn J. Hinton |
1991-06-11 |