Issued Patents All Time
Showing 25 most recent of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12253913 | Memory error tracking and logging | Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash, Era K. Nangia +1 more | 2025-03-18 |
| 12248369 | Decoding status flag techniques for memory circuits | Steven R. Hutsell, Gregory S. Mathews, Yi-Chun Chen, Kevin C. Wong, Kalpana Bansal | 2025-03-11 |
| 12243575 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Sukalpa Biswas | 2025-03-04 |
| 11934265 | Memory error tracking and logging | Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash, Era K. Nangia +1 more | 2024-03-19 |
| 11829242 | Data corruption tracking for memory reliability | Steven R. Hutsell, Gregory S. Mathews, Yi-Chun Chen, Kevin C. Wong, Kalpana Bansal | 2023-11-28 |
| 11830534 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Sukalpa Biswas | 2023-11-28 |
| 11468935 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Sukalpa Biswas | 2022-10-11 |
| 10929222 | Storing address of spare in failed memory location | Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox | 2021-02-23 |
| 10916290 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Sukalpa Biswas | 2021-02-09 |
| 10886273 | Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors | Rajesh N. Gupta, Scott Robins | 2021-01-05 |
| 10573368 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Sukalpa Biswas | 2020-02-25 |
| 10373956 | Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors | Rajesh N. Gupta, Scott Robins | 2019-08-06 |
| 10318377 | Storing address of spare in failed memory location | Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox | 2019-06-11 |
| 10042701 | Storing address of spare in failed memory location | Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox | 2018-08-07 |
| 9691465 | Thyristors, methods of programming thyristors, and methods of forming thyristors | Scott Robins, Rajesh N. Gupta | 2017-06-27 |
| 9520447 | Memory cells having a common gate terminal | Rajesh N. Gupta | 2016-12-13 |
| 9472279 | Memory cell dynamic grouping using write detection | Yi-Chun Shih | 2016-10-18 |
| 9361966 | Thyristors | Scott Robins, Rajesh N. Gupta | 2016-06-07 |
| 9082494 | Memory cells having a common gate terminal | Rajesh N. Gupta | 2015-07-14 |
| 8952418 | Gated bipolar junction transistors | Rajesh N. Gupta, Scott Robins | 2015-02-10 |
| 8576649 | Sense amplifiers and operations thereof | — | 2013-11-05 |
| 8576607 | Hybrid memory cell array and operations thereof | — | 2013-11-05 |
| 8519431 | Thyristors | Scott Robins, Rajesh N. Gupta | 2013-08-27 |
| 8441881 | Tracking for read and inverse write back of a group of thyristor-based memory cells | — | 2013-05-14 |
| 8093107 | Thyristor semiconductor memory and method of manufacture | Scott Robins, Kevin Yang | 2012-01-10 |