DU

Dirk Utess

GU Globalfoundries U.S.: 3 patents #166 of 665Top 25%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Overall (All Time): #911,809 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12324213 Stress layout optimization for device performance Zhixing Zhao, Dominik Martin Kleimaier, Irfan Saadat, Florent Ravaux 2025-06-03
11664432 Stress layout optimization for device performance Zhixing Zhao, Dominik Martin Kleimaier, Irfan Saadat, Florent Ravaux 2023-05-30
10923594 Methods to reduce or prevent strain relaxation on PFET devices and corresponding novel IC products Peter Steinmann, Stephanie Wilhelm 2021-02-16
9147618 Method for detecting defects in a diffusion barrier layer Frank Koschinsky, Bernd Hintze 2015-09-29
8598579 Test structure for ILD void testing and contact resistance measurement in a semiconductor device Dmytro Chumakov 2013-12-03