Issued Patents All Time
Showing 25 most recent of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411779 | High bandwidth memory system | Krishna T. Malladi, Hongzhong Zheng | 2025-09-09 |
| 12346286 | Two-dimensional processing array with a vertically stacked memory tile array | Shuangchen Li, Zhe Zhang, Hongzhong Zheng | 2025-07-01 |
| 12340101 | Scaling out architecture for dram-based processing unit (DPU) | Shuangchen Li, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng | 2025-06-24 |
| 12332828 | Graph acceleration solution with cloud FPGA | Shuangchen Li, Hongzhong Zheng, Zhe Zhang, Yuhao Wang | 2025-06-17 |
| 12271802 | Computing system for implementing artificial neural network models and method for implementing artificial neural network models | Tianchan GUAN, Shengcheng Wang, Hongzhong Zheng | 2025-04-08 |
| 12248402 | Bandwidth boosted stacked memory | Krishna T. Malladi, Mu-Tien Chang, Hongzhong Zheng | 2025-03-11 |
| 12242344 | DRAM assist error correction mechanism for DDR SDRAM interface | Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-Hyung Song, Jangseok Choi | 2025-03-04 |
| 12216537 | Error detection, prediction and handling techniques for system-in-package memory architectures | Tianchan GUAN, Hongzhong Zheng, Shuangchen Li | 2025-02-04 |
| 12216923 | Computer system, memory expansion device and method for use in computer system | Yijin GUAN, Tianchan GUAN, Hongzhong Zheng | 2025-02-04 |
| 12210768 | Flexible memory extension systems and methods | Yijin GUAN, Shengcheng Wang, Yuhao Wang, Shuangchen Li, Hongzhong Zheng | 2025-01-28 |
| 12197726 | 3D-stacked memory with reconfigurable compute logic | Mu-Tien Chang, Prasun Gera, Hongzhong Zheng | 2025-01-14 |
| 12189539 | Data processing system and memory management method of data processing system | Yijin GUAN, Tianchan GUAN, Shuangchen Li, Hongzhong Zheng | 2025-01-07 |
| 12189546 | Asynchronous communication protocol compatible with synchronous DDR protocol | Mu-Tien Chang, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi +1 more | 2025-01-07 |
| 12181987 | HBM RAS cache architecture | Krishna T. Malladi, Hongzhong Zheng | 2024-12-31 |
| 12164593 | Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning | Peng Gu, Krishna T. Malladi, Hongzhong Zheng | 2024-12-10 |
| 12153646 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Hongzhong Zheng | 2024-11-26 |
| 12147474 | System for graph node sampling and method implemented by computer | Tianchan GUAN, Shuangchen Li, Honzhong Zheng | 2024-11-19 |
| 12147341 | Memory controller prioritizing writing compressed data | Tianchan GUAN, Lide Duan, Hongzhong Zheng | 2024-11-19 |
| 12142338 | Memory priming and initialization systems and methods | Shuangchen Li, Tianchan GUAN, Hongzhong Zheng | 2024-11-12 |
| 12141227 | Adaptive matrix multiplication accelerator for machine learning and deep learning applications | Dongyan Jiang, Hongzhong Zheng | 2024-11-12 |
| 12124709 | Computing system and associated method | Tianchan GUAN, Yijin GUAN, Hongzhong Zheng | 2024-10-22 |
| 12073490 | Processing system that increases the capacity of a very fast memory | Yuhao Wang, Yijin GUAN, Shengcheng Wang, Shuangchen Li, Hongzhong Zheng | 2024-08-27 |
| 12056374 | Dynamic memory coherency biasing techniques | Lide Duan, Hongzhong Zheng | 2024-08-06 |
| 12032828 | Coordinated in-module RAS features for synchronous DDR compatible memory | Mu-Tien Chang, Hongzhong Zheng, Sun-Young Lim, Indong Kim, Jangseok Choi | 2024-07-09 |
| 12032497 | Scale-out high bandwidth memory system | Krishna T. Malladi, Hongzhong Zheng, Peng Gu | 2024-07-09 |