Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11797742 | Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design | Jiri Prevratil, Harsh Chilwal, Shreedhar Ramachandra, Prasenjit Biswas | 2023-10-24 |
| 9626468 | Assertion extraction from design and its signal traces | Eduard Cerny, Saptarshi Ghosh, Yogesh Pandey | 2017-04-18 |