| 7180802 |
Method of stress-testing an isolation gate in a dynamic random access memory |
— |
2007-02-20 |
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Method of stress-testing an isolation gate in a dynamic random access memory |
— |
2006-02-14 |
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System for testing integrated circuit devices |
Joseph C. Sher, Huy T. Vo, Nicholas M. van Heel, Victor Wong, Hua Zheng |
2005-08-16 |
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DRAM array and computer system |
— |
2005-03-22 |
| 6756805 |
System for testing integrated circuit devices |
Joseph C. Sher, Huy T. Vo, Nicholas M. van Heel, Victor Wong, Hua Zheng |
2004-06-29 |
| 6735132 |
6F2 DRAM array with apparatus for stress testing an isolation gate and method |
— |
2004-05-11 |
| 6590817 |
6F2 DRAM array with apparatus for stress testing an isolation gate and method |
— |
2003-07-08 |
| 6510533 |
Method for detecting or repairing intercell defects in more than one array of a memory device |
Tim Damon |
2003-01-21 |
| 6496027 |
System for testing integrated circuit devices |
Joseph C. Sher, Huy T. Vo, Nicholas Heel, Victor Wong, Hua Zheng |
2002-12-17 |
| 6167541 |
Method for detecting or preparing intercell defects in more than one array of a memory device |
Tim Damon |
2000-12-26 |
| 6066870 |
Single digit line with cell contact interconnect |
— |
2000-05-23 |
| 5986955 |
Method and apparatus for hiding data path equilibration time |
Rajesh Somasekharan |
1999-11-16 |
| 5866928 |
Single digit line with cell contact interconnect |
— |
1999-02-02 |
