| 5631485 |
ESD and hot carrier resistant integrated circuit structure |
Yi Wei, Ying-Tsong Loh, Chenming Hu |
1997-05-20 |
| 5496751 |
Method of forming an ESD and hot carrier resistant integrated circuit structure |
Yi Wei, Ying-Tsong Loh, Chenming Hu |
1996-03-05 |
| 5444003 |
Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure |
Ying-Tsong Loh, Ho-Yuan Yu |
1995-08-22 |
| 5411906 |
Method of fabricating auxiliary gate lightly doped drain (AGLDD) structure with dielectric sidewalls |
Eric A. Johnson, Ying-Tsong Loh |
1995-05-02 |
| 5340761 |
Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure |
Ying-Tsong Loh |
1994-08-23 |
| 5288652 |
BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure |
Ying-Tsong Loh, Edward D. Nowak |
1994-02-22 |
| 5227320 |
Method for producing gate overlapped lightly doped drain (GOLDD) structure for submicron transistor |
Eric A. Johnson, Ying-Tsong Loh, Yoshiko H. Strunk |
1993-07-13 |
| 5196357 |
Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor |
William J. Boardman, Ying-Tsong Loh, Edward D. Nowak |
1993-03-23 |
| 4574177 |
Plasma etch method for TiO.sub.2 |
— |
1986-03-04 |
| 4521446 |
Method for depositing polysilicon over TiO.sub.2 |
Donald J. Coleman, Roger A. Haken |
1985-06-04 |