Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8901959 | Hybrid IO cell for wirebond and C4 applications | Rohit Shetty | 2014-12-02 |
| 6377098 | CMOS latch having a selectable feedback path | — | 2002-04-23 |
| 5925143 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Ravi Kolagotla, Dennis A. Miller, Maria Noack, Steven F. Oakland +2 more | 1999-07-20 |
| 5719879 | Scan-bypass architecture without additional external latches | Pamela S. Gillis, Ravi Kolagotla, Dennis A. Miller, Maria Noack, Steven F. Oakland +2 more | 1998-02-17 |
| 5030856 | Receiver and level converter circuit with dual feedback | Allan H. Dansky, Dennis C. Reedy | 1991-07-09 |