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Method for protecting STI structures with low etching rate liners |
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2003-02-11 |
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Method of forming self-aligned unlanded via holes |
Hua-Shu Wu, Hung-Chan Lin |
2001-02-13 |
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Method for forming via holes |
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Method for manufacturing MOS device with adjustable source/drain extensions |
— |
1999-12-21 |
| 5986310 |
Prolonging a polysilicon layer in smaller memory cells to prevent polysilicon load punch through |
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1999-11-16 |
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High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom |
Chih-Ming Chen, Wen-Ying Wen |
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Method for reducing antenna effect during plasma etching procedure for semiconductor device fabrication |
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