Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10853544 | Selective execution for partitioned parallel simulations | Ramesh Narayanaswamy, Paraminder S. Sahai | 2020-12-01 |
| 8849644 | Parallel simulation using an ordered priority of event regions | Chong Guan Tan | 2014-09-30 |
| 6487704 | System and method for identifying finite state machines and verifying circuit designs | Michael T. McNamara, Chong Guan Tan, David Massey | 2002-11-26 |
| 5678028 | Hardware-software debugger using simulation speed enhancing techniques including skipping unnecessary bus cycles, avoiding instruction fetch simulation, eliminating the need for explicit clock pulse generation and caching results of instruction decoding | Mikhail Bershteyn, Ross T. Casley, Abhijit Ghosh, Anurag Mithalal Jain, Michael Leigh Lipsie +2 more | 1997-10-14 |