Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12047590 | Transmission bit-rate control in a video encoder | Soyeb Nagori, Naveen Srinivasamurthy | 2024-07-23 |
| 11997287 | Methods and systems for encoding of multimedia pictures | Arun Shankar Kudana, Uday Pudipeddi Kiran, Soyeb Nagori | 2024-05-28 |
| 11451799 | Transmission bit-rate control in a video encoder | Soyeb Nagori, Naveen Srinivasamurthy | 2022-09-20 |
| 11182160 | Generating source and destination addresses for repeated accelerator instruction | Maik Brett, Christian Tuschen, Sidhartha Taneja, Tejbal Prasad, Saurabh Arora +3 more | 2021-11-23 |
| 10827184 | Methods and systems for encoding of multimedia pictures | Arun Shankar Kudana, Uday Pudipeddi Kiran, Soyeb Nagori | 2020-11-03 |
| 10764591 | Transmission bit-rate control in a video encoder | Soyeb Nagori, Naveen Srinivasamurthy | 2020-09-01 |
| 10593019 | Method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images | Ravindranath Ramalingaiah Munnan, Venkata Ravisankar Jayanthi, Rajat Agarwal, Ashish Ranjan, Joy Dutta +5 more | 2020-03-17 |
| 10229478 | Image processing apparatus and image processing method | Bindigan Hariprasanna Pawan Prasad, Venkat Ramana Peddigari, Gayathri Ramanujam, Phanish Hanagal Srinivasa Rao, Loka Sudharsan Reddy +2 more | 2019-03-12 |
| 9888244 | Methods and systems for encoding of multimedia pictures | Arun Shankar Kudana, Uday Pudipeddi Kiran, Soyeb Nagori | 2018-02-06 |
| 8472527 | Hierarchical motion estimation using original frame for sub-sampled reference | Venugopala K. Madumbu, Raghavendra Kudva, Pramod Kumar Swami | 2013-06-25 |
| 8213511 | Video encoder software architecture for VLIW cores incorporating inter prediction and intra prediction | Pramod Kumar Swami, Venugopala K. Madumbu, Jacques Michel Bride, David Gottardo | 2012-07-03 |
| 7778494 | FIR-based interpolation in advanced video codecs on VLIW processor | Pavan Venkata Shastry, Sunand Mittal, Ratna M. V. Reddy | 2010-08-17 |
| 5678028 | Hardware-software debugger using simulation speed enhancing techniques including skipping unnecessary bus cycles, avoiding instruction fetch simulation, eliminating the need for explicit clock pulse generation and caching results of instruction decoding | Mikhail Bershteyn, Ross T. Casley, Chiahon Chien, Abhijit Ghosh, Michael Leigh Lipsie +2 more | 1997-10-14 |