CT

Chong Guan Tan

VD Verisity Design: 3 patents #1 of 7Top 15%
MG Mentor Graphics: 1 patents #345 of 698Top 50%
📍 Saratoga, CA: #1,351 of 2,933 inventorsTop 50%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,222,347 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
8849644 Parallel simulation using an ordered priority of event regions Chiahon Chien 2014-09-30
6687662 System and method for automated design verification Michael T. McNamara, David Massey 2004-02-03
6487704 System and method for identifying finite state machines and verifying circuit designs Michael T. McNamara, Chiahon Chien, David Massey 2002-11-26
6141630 System and method for automated design verification Michael T. McNamara, David Massey 2000-10-31