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Hardware accelerator test harness generation |
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Structured block transfer module, system architecture, and method for transferring |
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2016-10-04 |
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Structured block transfer module, system architecture, and method for transferring |
Roberto Attias, William Charles Jordan, Stephen John Joseph Fricke, Akash R. Deshpande, Navendu Sinha +2 more |
2016-08-30 |
| 9003166 |
Generating hardware accelerators and processor offloads |
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2015-04-07 |
| 8706987 |
Structured block transfer module, system architecture, and method for transferring |
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2014-04-22 |
| 8289966 |
Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data |
Stephen John Joseph Fricke, William Charles Jordan, Roberto Attias, Akash R. Deshpande, Navendu Sinha +2 more |
2012-10-16 |
| 8161429 |
Methods and apparatus for initializing serial links |
Allen Chan, Faisal Dada, Karl Lu, Samson Min Rong Tan, Venkat Yadavalli +1 more |
2012-04-17 |
| 8127113 |
Generating hardware accelerators and processor offloads |
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2012-02-28 |
| 8073040 |
Serial communications control plane with optional features |
Allen Chan, Faisal Dada, Karl Lu, Venkat Yadavalli, Arye Ziklik |
2011-12-06 |
| 7719970 |
Serial communications system with optional data path and control plane features |
Faisal Dada, Kari Lu, Venkat Yadavalli, Arye Ziklik |
2010-05-18 |
| 7356756 |
Serial communications data path with optional features |
Allen Chan, Faisal Dada, Karl Lu, Venkat Yadavalli, Arye Ziklik |
2008-04-08 |
| 7228509 |
Design tools for configurable serial communications protocols |
Faisal Dada, Karl Lu, Arye Ziklik |
2007-06-05 |
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Block clock and initialization circuit for a complex high density PLD |
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1998-09-22 |
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Programmable logic device with multi-level power control |
Bradley A. Sharpe-Geisler |
1998-05-12 |
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Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation |
Om P. Agrawal, Bradley A. Sharpe-Geisler, Nicholas A. Schmitz |
1996-05-28 |