Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11527991 | Circuit for extended voltage control oscillator gain linearity | Akarsh Joshi | 2022-12-13 |
| 11223469 | System for serializing high speed data signals | Ravi Mehta | 2022-01-11 |
| 11101830 | Calibration scheme for serialization in transmitter | Shourya Kansal, Ravi Mehta | 2021-08-24 |
| 10972105 | Clock generation and correction circuit | — | 2021-04-06 |
| 10715158 | Phase-locked loop (PLL) with calibration circuit | Akarsh Joshi, Sharath Nadsar | 2020-07-14 |
| 10659214 | Multi-level clock and data recovery circuit | Ravi Mehta, Sanket Naik, Jayesh Wadekar | 2020-05-19 |
| 10608645 | Fast locking clock and data recovery circuit | Ravi Mehta | 2020-03-31 |
| 10516523 | System for serializing high speed data signals | Ravi Mehta | 2019-12-24 |
| 10491367 | Clock and data recovery (CDR) circuit | Ravi Mehta | 2019-11-26 |
| 10361706 | Clock and data recovery (CDR) circuit | Jairaj Naik K R | 2019-07-23 |
| 10236891 | Lock time measurement of clock and data recovery circuit | Ravi Mehta, Manjunath Shet SN, Vishal Dilipbhai Nimbark | 2019-03-19 |
| 10236843 | High gain differential amplifier with common-mode feedback | Jayesh Wadekar, Ravi Mehta | 2019-03-19 |
| 10205445 | Clock duty cycle correction circuit | Shourya Kansal, Ravi Mehta, Jayesh Wadekar | 2019-02-12 |
| 10164798 | Driver circuit for transmitter | Ravi Mehta | 2018-12-25 |
| 10142097 | System for serializing high speed data signals | Ravi Mehta | 2018-11-27 |
| 9813069 | Half-rate bang-bang phase detector | Ravi Mehta | 2017-11-07 |
| 9577848 | Decision feedback equalizer | Ravi Mehta, Rajesh V. | 2017-02-21 |
| 9548855 | Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit | Sujoy Chakravarty, Ravi Mehta, Gopalkrishna Ullal Nayak | 2017-01-17 |
| 9509319 | Clock and data recovery circuit | Ravi Mehta, Gopal Krishna Ullal Nayak, Sharath Bhat N | 2016-11-29 |
| 9407424 | Fast locking clock and data recovery using only two samples per period | Bharathi Rahuldev Holla, Jagdish Chand Goyal, Sujoy Chakravarty, Sumantra Seth | 2016-08-02 |
| 9407249 | System and method for pulse width modulation | Sumantra Seth, Uttam Kumar Patro, Jagdish Chand Goyal | 2016-08-02 |
| 7719369 | Sigma delta digital to analog converter with wide output range and improved linearity | Anant Shankar Kamath | 2010-05-18 |