Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7737487 | Nonvolatile memories with tunnel dielectric with chlorine | Zhong Dong | 2010-06-15 |
| 7371695 | Use of TEOS oxides in integrated circuit fabrication processes | Tai-Peng Lee | 2008-05-13 |
| 7355239 | Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches | Yi Ding | 2008-04-08 |
| 7300745 | Use of pedestals to fabricate contact openings | Chia-Shun Hsiao, Chunchieh Huang, Jin Ho Kim, Kuei-Chang Tsai, Daniel Wang | 2007-11-27 |
| 7071115 | Use of multiple etching steps to reduce lateral etch undercut | Chunchieh Huang, Chia-Shun Hsiao, Jin Ho Kim, Kuei-Chang Tsai, Daniel Wang | 2006-07-04 |
| 7037792 | Formation of removable shroud by anisotropic plasma etch | John Lee | 2006-05-02 |
| 6955964 | Formation of a double gate structure | John Lee | 2005-10-18 |
| 6933218 | Low temperature nitridation of amorphous high-K metal-oxide in inter-gates insulator stack | Tai-Peng Lee | 2005-08-23 |
| 6846730 | Two stage etching of silicon nitride to form a nitride spacer | John Lee | 2005-01-25 |
| 6794303 | Two stage etching of silicon nitride to form a nitride spacer | John Lee | 2004-09-21 |
| 6566196 | Sidewall protection in fabrication of integrated circuits | Chia-Shun Hsiao, Chunchieh Huang, Jin Ho Kim, Chung Wai Leung, Kuei-Chang Tsai | 2003-05-20 |
| 6121154 | Techniques for etching with a photoresist mask | John Lee, Chau Arima, Eddie Chiu | 2000-09-19 |