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Order enforcement for delegable memory accesses |
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Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length |
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Cracking instructions into a plurality of micro-operations |
Quentin Éric NOUVEL, Luca NASSI, Nicola Piano, Geoffray Matthieu Lacourba |
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Controlling use of data determined by a resolve-pending speculative operation |
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Register freeing latency |
Luca NASSI, Geoffray Matthieu Lacourba, Cedric Denis Robert Airaud |
2024-10-08 |
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Peter Richard Greenhalgh, Frederic Claude Marie Piry, Ian Michael Caulfield |
2023-10-31 |
| 11748101 |
Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations |
Abhishek Raja |
2023-09-05 |
| 11720494 |
Cache eviction control for a private cache in an out-of-order data processing apparatus |
Yohan Fernand Fargeix, Lucas Garcia, Luca NASSI |
2023-08-08 |
| 11709782 |
Memory address translation |
Paolo Monti, Abdel Hadi MOUSTAFA, Vincenzo Consales, Abhishek Raja |
2023-07-25 |
| 11550620 |
Task dispatch |
Hakan Persson, Frederic Claude Marie Piry, Matthew Evans |
2023-01-10 |
| 11526615 |
Speculative side-channel hint instruction |
Peter Richard Greenhalgh, Frederic Claude Marie Piry, Ian Michael Caulfield |
2022-12-13 |
| 11397584 |
Tracking speculative data caching |
Ian Michael Caulfield, Peter Richard Greenhalgh, Frederic Claude Marie Piry |
2022-07-26 |
| 11392383 |
Apparatus and method for prefetching data items |
Ian Michael Caulfield, Peter Richard Greenhalgh, Frederic Claude Marie Piry |
2022-07-19 |
| 11340901 |
Apparatus and method for controlling allocation of instructions into an instruction cache storage |
Frederic Claude Marie Piry, Peter Richard Greenhalgh, Ian Michael Caulfield |
2022-05-24 |
| 11263133 |
Cache control in presence of speculative read operations |
Andreas Lars Sandberg, Stephan Diestelhorst, Nikos NIKOLERIS, Ian Michael Caulfield, Peter Richard Greenhalgh +1 more |
2022-03-01 |
| 11231932 |
Transactional recovery storage for branch history and return addresses to partially or fully restore the return stack and branch history register on transaction aborts |
Guillaume Bolbenes, Houdhaifa BOUZGUARROU |
2022-01-25 |
| 11221951 |
Skipping tag check for tag-checked load operation |
Abhishek Raja, Kias Magnus Bruce |
2022-01-11 |
| 11157277 |
Data processing apparatus with respective banked registers for exception levels |
Cedric Denis Robert Airaud, Luca NASSI, Rémi Marius Teyssier |
2021-10-26 |
| 11132202 |
Cache control circuitry and methods |
Luca NASSI, Rémi Marius Teyssier, Cedric Denis Robert Airaud, François Donati, Christophe Laurent Carbonne +1 more |
2021-09-28 |
| 11126714 |
Encoding of input to storage circuitry |
Alastair David Reid, Dominic Phillip MULLIGAN, Milosch Meriac, Matthias Lothar Boettcher, Nathan Yong Seng Chong +5 more |
2021-09-21 |
| 10977044 |
Executing branch instructions following a speculation barrier instruction |
Rémi Marius Teyssier, Luca NASSI, François Donati |
2021-04-13 |
| 10831499 |
Apparatus and method for performing branch prediction |
Houdhaifa BOUZGUARROU, Guillaume Bolbenes, Frederic Claude Marie Piry |
2020-11-10 |
| 10635445 |
Handling modifications to permitted program counter ranges in a data processing apparatus |
Rémi Marius Teyssier, Cedric Denis Robert Airaud, Luca NASSI, Guillaume Bolbenes, François Donati +2 more |
2020-04-28 |
| 10558462 |
Apparatus and method for storing source operands for operations |
Luca NASSI, Cedric Denis Robert Airaud, Rémi Marius Teyssier |
2020-02-11 |
| 10394716 |
Apparatus and method for controlling allocation of data into a cache storage |
Frederic Claude Marie Piry, Peter Richard Greenhalgh, Ian Michael Caulfield, Jeffrey Kehl |
2019-08-27 |