Issued Patents All Time
Showing 25 most recent of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9413363 | Charge pump with matched currents | Simon Bass | 2016-08-09 |
| 9397648 | Systems, circuitry, and methods for decoding pulse width modulated signal | Tomer Shaul Elran | 2016-07-19 |
| 8922176 | Programmable slew rate power switch | Tomer Shaul Elran | 2014-12-30 |
| 8799839 | Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects | Richard A. Laubhan | 2014-08-05 |
| 8775995 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Ruben Molina | 2014-07-08 |
| 8694937 | Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same | Rich Laubhan, Joseph J. Jamann, Bruce E. Zahn | 2014-04-08 |
| 8645888 | Circuit timing analysis incorporating the effects of temperature inversion | — | 2014-02-04 |
| 8539424 | System and method for designing integrated circuits that employ adaptive voltage scaling optimization | — | 2013-09-17 |
| 8516424 | Timing signoff system and method that takes static and dynamic voltage drop into account | Hyuk-Jong Yi | 2013-08-20 |
| 8473890 | Timing error sampling generator and a method of timing testing | Sreejit Chakravarty | 2013-06-25 |
| 8397196 | Intelligent dummy metal fill process for integrated circuits | — | 2013-03-12 |
| 8332792 | Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same | Joseph J. Jamann, Rich Laubhan, Bruce E. Zahn | 2012-12-11 |
| 8321826 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Ruben Molina | 2012-11-27 |
| 8225257 | Reducing path delay sensitivity to temperature variation in timing-critical paths | — | 2012-07-17 |
| 8191029 | Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing | Sreejit Chakravarty | 2012-05-29 |
| 8181144 | Circuit timing analysis incorporating the effects of temperature inversion | — | 2012-05-15 |
| 8010935 | Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit | Sreejit Chakravarty | 2011-08-30 |
| 7971169 | System and method for reducing the generation of inconsequential violations resulting from timing analyses | Sreejit Chakravarty, Nicholas Callegari | 2011-06-28 |
| 7739639 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Ruben Molina | 2010-06-15 |
| 7480881 | Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction | Ruben Molina, Subodh Yashwant Bhike | 2009-01-20 |
| 7370309 | Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints | — | 2008-05-06 |
| 7213223 | Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism | — | 2007-05-01 |
| 7178121 | Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design | — | 2007-02-13 |
| 7174524 | Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring | Benjamin Mbouombouo | 2007-02-06 |
| 7107558 | Method of finding critical nets in an integrated circuit design | Maad Al-Dabagh | 2006-09-12 |